Field of the Invention
The invention relates to a method for fabricating a dynamic memory cell in a semiconductor substrate having a trench capacitor and a selection transistor, and to a semiconductor memory having such a memory cell.
In dynamic random access memories (DRAMs), use is predominantly made of one-transistor memory cells which are each composed of a selection transistor and a storage capacitor, the information being stored in the storage capacitor in the form of electric charges. In this case, a DRAM memory comprises a matrix of such memory cells which are connected up in the form of rows and columns. Usually, the row connections are designated as word lines and the column lines are designated as bit lines. In this case, the selection transistor and the storage capacitor in the memory cell are connected to one another in such a way that when the selection transistor is driven via a word line, the charge of the storage capacitor can be read in and out via a bit line.
The one-transistor memory cell must satisfy essentially three basic requirements. The storage capacitor must have a sufficiently large storage capacitance of approximately 25 to 40 fF per cell, in order to obtain reliable charge detection of the stored charge and thus an adequate read signal. On account of the increasing miniaturization, it is furthermore necessary to create a packing-dense cell layout which is convenient for fastening and with which the area requirement for the memory cell can be greatly limited. Furthermore, it is necessary that, on the one hand, a sufficient current flows via the selection transistor for reading the storage charges in and out into the storage capacitor and, on the other hand, the selection transistor reliably blocks in the switched-off state. In particular, these parameters of the selection transistor must not be adversely affected by a very close proximity to the storage capacitor or by the required contact between the selection transistor and the storage capacitor.
One focus of attention in the technological development of DRAM memories is the storage capacitor. In order to provide for an adequate storage capacitance in the context of the continually decreasing cell area from technology generation to technology generation for the memory cell, storage capacitors which utilize the third dimension have been developed. Such three-dimensional storage capacitors are often embodied as trench capacitors in DRAM cells. In the case of such trench capacitors, a trench is etched into the semiconductor substrate and is filled with a dielectric layer and a first storage electrode, a doped region of the semiconductor substrate serving as second storage electrode. The selection transistor of the DRAM cell is then usually formed on the planar semiconductor surface by the trench capacitor.
On account of the advancing miniaturization of the memory cells, even in the case of the trench capacitors further possibilities are sought for simultaneously reducing the area requirement and increasing the capacitor capacitance. One possibility is to increase the depth of the trenches in order to obtain a larger capacitor capacitance. Technological limits are imposed in this case, however, on account of very high aspect ratios (ratio of trench depth to trench width). As an alternative and in addition to further deepening of the trenches, methods are used which allow the surface area within the trench capacitor to be increased by additional extension in the lower trench region. However, the etching processes required for such extension of the trenches likewise encounters technological limits.
Furthermore, for the purpose of increasing the capacitance in trench capacitors, very thin storage dielectrics having a high dielectric constant are also used as dielectric intermediate layers between the capacitor electrodes and materials which are distinguished by a particularly high conductivity are chosen for the capacitor electrodes.
In addition to the further development of the trench capacitors, however, the selection transistor of the memory cell is also the subject of technological development. In order to increase the performance of the selection transistor in the memory cell, the doping profiles for forming the electrode regions and the channel region and also the well bounding the selection transistor are optimized. In addition, use is also made of improved insulator layers for delimiting the channel region from the gate region and optimizations of the thermal budget are performed. Additional approaches involve avoiding defects in the formation of the selection transistor in the semiconductor substrate and improved processes for the connection of the electrode regions of the selection transistors by low-impedance connection contacts.
A further objective in improving the memory cells is to avoid reciprocal influencing of trench capacitor and selection transistor due to their very close proximity. In this case, there is the risk of a parasitic transistor being formed along the trench capacitor. In order to eliminate such a parasitic transistor, use is made, in particular, of a thick oxide collar for insulating the outer capacitor electrode from the selection transistor. This has the disadvantage that it is necessary to produce a deep trench for the trench capacitor with a correspondingly high aspect ratio.
U.S. Pat. No. 6,236,079 B1 discloses a method for fabricating a dynamic memory cell and a corresponding semiconductor memory having a dynamic memory cell in accordance with the preamble of claims 1 and 5, respectively. IBM Disclosure Bulletin, Vol. 32, No. 3B, pages 163 to 168, describes a similar method and a similar semiconductor memory. Further relevant fabrication methods and semiconductor memories are presented in U.S. Pat. No. 5,914,510, U.S. Pat. No. 5,627,092 and U.S. Pat. No. 5,442,211.
It is an object of the present invention to provide a method for fabricating a dynamic memory cell in a semiconductor substrate and a corresponding memory cell in which particularly small trench diameters can be achieved whilst maintaining the storage capacitance, at the same time the performance of the selection transistor not being impaired by the proximity to the trench capacitor.
This object is achieved by means of a method according to claim 1 and a semiconductor memory according to claim 5. Preferred refinements are specified in the dependent claims.
According to the invention, a dielectric insulator layer is formed between a selection transistor and a trench capacitor, a first electrode region of the selection transistor essentially being arranged above a block-type layer electrode of the trench capacitor and being connected to said electrode via a contact opening in the dielectric insulator layer, said contact opening being provided with an electrically conductive filling layer.
The configuration according to the invention with a dielectric insulation layer between the selection transistor and the trench capacitor makes it possible for these two active components in the memory cell to be completely electrically isolated from one another with the exception of the contact-connection via the electrically conductive filling layer and thus for the risk of a vertical parasitic transistor between the selection transistor and the trench capacitor to be reliably prevented. In particular, the dielectric layer makes it possible to dispense with an insulation collar which is usually formed at the upper section of the trench in the trench capacitor in order to prevent a parasitic transistor between the selection transistor and the trench capacitor, so that essentially the entire depth of the trench can be utilized as active memory area. As a result of this, compared with conventional trench capacitors with an insulation collar, whilst ensuring the same capacitor capacitance, trenches with a smaller aspect ratio can be formed, as a result of which the fabrication process can be significantly simplified. A further simplification of the fabrication process is also achieved by virtue of the fact that the time-consuming and expensive process required for forming the insulation collar in the case of conventional trench capacitors can be dispensed with in favor of a simple process of deposition of an insulation layer.
According to the invention, the dielectric insulator layer between the selection transistor and the trench capacitor is produced with the aid of the wafer bonding method. This wafer bonding method, in which preferably a first thin insulator layer is applied to the semiconductor substrate provided with the trench capacitor and a second semiconductor substrate is furthermore provided with a second thin dielectric insulator layer, the two semiconductor substrates with their insulator layers being brought one on top of the other in order to produce a mechanically fixed connection between the dielectric insulator layers by wafer bonding, makes it possible to produce a particularly thin and uniform dielectric insulator layer between the selection transistor and the trench capacitor.
In accordance with one preferred embodiment, the selection transistor is formed in the second semiconductor substrate used, after the wafer bonding method. This makes it possible to fabricate the selection transistor using SOI technology, with which transistors having a particularly fast switching behavior can be produced.
In accordance with a further preferred embodiment, the contact opening provided with a dielectric filling layer is formed in a self-aligning manner between the first electrode region of the selection transistor and the block-type inner electrode of the trench capacitor, the insulation encapsulation of the word line region of the selection transistor preferably being used as an etching mask for forming the contact opening. As a result of this, the contact-connection between the selection transistor and the trench capacitor can be realised in a simple manner. The invention is explained in more detail with reference to the accompanying drawings.